Multilevel interconnect transfer process

Details Multilevel interconnect transfer process Multilevel interconnect transfer process

1987-07-24

1988-05-10

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437195, 437183, 148DIG135, 357 80, 439 67, 361398, H01L 21283, H01L 21316

Patent

active

047435682

ABSTRACT:
A method for processing multilevel interconnect lines separately from the multichip module on which they are to be employed. An oxide layer (16) is grown on a silicon wafer (14) and followed by a polyimide layer (18). Then a metal layer (20) is deposited and patterned. This is followed by another polyimide layer (24) having vias and another patterned metal layer (28). The vias allow for connections to be made between metal layers. Many polyimides and metal layers may be processed to allow for the desired number of levels of interconnect lines. After a last polyimide layer (32) is deposited, the oxide layer is etched to separate the multilevel interconnect line transfer (34) from the silicon wafer. After the processing of the multilevel interconnect lines, the multilevel interconnect line transfer is adhered to the multichip module in a predetermined relationship and electrical connections are made between them. In an alternative embodiment, a boron nitride layer (46) is bonded on a surface of silicon wafer (14). Stabilizing ring (44) is bonded on a second surface of the silicon wafer. Exposed regions of the wafer are etched away. The processing of multilevel interconnect line transfer (34) occurs on boron nitride layer (46) in the same manner as previously described.

REFERENCES:
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patent: 4420203 (1983-12-01), Dry et al.
patent: 4446477 (1984-05-01), Currie et al.
patent: 4480288 (1984-10-01), Gazdik et al.
patent: 4630096 (1986-12-01), Drye et al.
patent: 4698662 (1987-10-01), Young et al.

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