Method for fabricating an NPN transistor of minimum surface

Details Method for fabricating an NPN transistor of minimum surface Method for fabricating an NPN transistor of minimum surface

1997-11-13

1999-03-09

Bowers, Charles

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

H01L 21331, H01L 218222

Patent

active

058800000

ABSTRACT:
The present invention relates to an NPN transistor, the base and the emitter of which are formed within a window defined in a thick oxide according to a first substantially rectangular mask. At least a portion of the area defined by the first mask is covered with a polysilicon layer, preferably along a side of this first mask, a base contact area being formed under this polysilicon layer, the three other sides of the emitter-base area being delimited by a protection layer, an intrinsic base area, and then an emitter area covered with a doped N-type polysilicon layer, being formed in the opening thus defined.

REFERENCES:
patent: 4215418 (1980-07-01), Muramatsu
patent: 4276543 (1981-06-01), Miller et al.
patent: 5439832 (1995-08-01), Nakamura

Affiliated with

Also associated with

Rating

Method for fabricating an NPN transistor of minimum surface does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating an NPN transistor of minimum surface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating an NPN transistor of minimum surface will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1320361