Planarizing by polishing techniques for fabricating semiconducto

Details Planarizing by polishing techniques for fabricating semiconducto Planarizing by polishing techniques for fabricating semiconducto

1994-12-12

1996-09-10

Dang, Thi

Fishing, trapping, and vermin destroying

437228, 437238, 437978, 1566261, 1566361, H01L 2100

Patent

active

055545556

ABSTRACT:
Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into, the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.

REFERENCES:
patent: 5069002 (1991-12-01), Sandhu et al.
patent: 5252504 (1993-10-01), Lowrey et al.

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