CMOS single input buffer for multiplexed inputs

Details CMOS single input buffer for multiplexed inputs CMOS single input buffer for multiplexed inputs

1990-07-31

1993-03-02

Popek, Joseph A.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36523002, G11C 700

Patent

active

051915553

ABSTRACT:
An input buffer circuit is disclosed. The circuit has a single stage circuit portion for receiving a multiplexed row address bit and a multiplexed column address bit. Circuitry is connected to the single stage circuit portion for separately holding the received multiplexed row address bit and the received multiplexed column address bit. The single stage circuit portion may include a tri-state inverter having a tri-state control input coupled to an input buffer control signal and a latch to hold the output of the tri-state inverter when it is tri-stated by the input buffer control signal. The first circuit portion may be of the CMOS type. Such a circuit is useful in the memory support circuitry of an integrated circuit of the dynamic random access memory type.

REFERENCES:
patent: 4541078 (1985-09-01), Dumbri et al.
patent: 4636986 (1987-01-01), Pinkham

Affiliated with

Also associated with

Rating

CMOS single input buffer for multiplexed inputs does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS single input buffer for multiplexed inputs, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS single input buffer for multiplexed inputs will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-131763