Non-volatile semiconductor memory device with transistor paralle

Details Non-volatile semiconductor memory device with transistor paralle Non-volatile semiconductor memory device with transistor paralle

1991-11-27

1993-03-02

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular biasing

36518911, 365218, 36523006, 257316, G11C 1140

Patent

active

051915510

ABSTRACT:
A non-volatile semiconductor memory device is formed by a plurality of memory cell array groups arranged in a matrix form. Each of the memory cell array groups includes a transistor group. The transistor group is composed of a plurality of transistor pairs connected in series, the transistor pair being formed by a memory transistor and a first selecting transistor connected in parallel with each other. At least one second selecting transistor is connected between a bit line and the transistor group. The memory transistor is over-layered above the first selecting transistor. Such an arrangement of the non-volatile semiconductor memory device does not require an intermediate potential for selective write, so that the write can be made at a relatively low voltage, can avoid the problems of an excess write and an excess erasure, has a wide voltage margin for write/erasure, can be easily fabricated even if the first gate insulating film is thick, and has the functions of a word write and a word erasure.

REFERENCES:
patent: 4580247 (1986-04-01), Adam
patent: 4677590 (1987-06-01), Arakawa
patent: 4807188 (1989-02-01), Casagrande
patent: 4896298 (1990-01-01), Kowalski
patent: 4996669 (1991-02-01), Endoh et al.
patent: 5075890 (1991-12-01), Itoh et al.
patent: 5105386 (1992-04-01), Andoh et al.

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