Fishing – trapping – and vermin destroying
Patent
1990-04-16
1991-07-16
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437200, 437 34, 748DIG106, H01L 21336
Patent
active
050325370
ABSTRACT:
The present invention relates to a method of manufacturing a semiconductor device. In a semiconductor substrate formed with a first semiconductor region of P-type and a second semiconductor region of N-type and an insulating film formed between and extending into the first and the second semiconductor regions, gate electrodes of a laminate of a polysilicon layer and a silicide layer are formed on the insulating film covering the first and the second semiconductor regions. A gate electrode situated on the first semiconductor region has an end portion facing and spaced from an end portion of a gate electrode situated on the second semiconductor region. A masking layer is formed on the second semiconductor region with an edge of the masking layer falling between the two gate electrodes where the two end portions face each other. The first semiconductor region is doped with an impurity of N-type, thereby forming a third semiconductor region in the first semiconductor region. The masking layer is removed from the second semiconductor region and a masking layer is formed on the first semiconductor region with an edge of the masking layer falling between the two gate electrodes where the two end portions face each other. The second semiconductor region is doped with an impurity of P-type, thereby forming a fourth semiconductor region in the second semiconductor region. By providing a masking layer to fall between the end portions of the gate electrodes, the gate electrodes are discretely doped with either the N-type impurity or the P-type impurity to form discrete semiconductor regions.
REFERENCES:
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patent: 4859630 (1989-08-01), Josquin
Kudo Satoshi
Yoshizumi Keiichi
Hearn Brian E.
Hitachi , Ltd.
Quach T. N.
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