Trench gate VCMOS method of manufacture

Details Trench gate VCMOS method of manufacture Trench gate VCMOS method of manufacture

1990-06-05

1991-07-16

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 27, 437 30, 437 34, 437 40, 437 57, 437 62, 437 33, 148DIG10, H01L 2176, H01L 21266

Patent

active

050325299

ABSTRACT:
VMOS transistors are formed with gate segments in dielectric trenches separating islands formed on a common dielectric base. A trench gate may be common for VMOS at opposed edges of adjacent islands, for VMOS at common edge of common islands or for VMOSs at uncommon edges of common islands. Common regions of an island may be used to form parallel or series VMOS with separate trench gates. The trenches may be formed after device region formation. Isolated gate segments may be formed by removing portions of dielectrically filled trenches to form recesses to be filled with gate material or forming gate material filled dielectric trenches and removing portions of the gate material and refilling with dielectric to form the isolated gate segments.

REFERENCES:
patent: 3893155 (1975-07-01), Ogiue
patent: 4117587 (1978-10-01), Kano et al.
patent: 4408304 (1983-10-01), Nishizawa et al.
patent: 4516313 (1985-05-01), Turi et al.
patent: 4751561 (1988-06-01), Jastrzebski
"High Performance Lateral PNP Structure", IBM Technical Disclosure Bulletin, vol. 27, No. 11, 4/1985.
"High Performance PNP and NPN Bipolar Chip", IBM Technical Disclosure Bulletin, vol. 23, No. 7B, 12/1980.

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