Resistor structure in integrated injection logic

Details Resistor structure in integrated injection logic Resistor structure in integrated injection logic

1983-12-22

1986-01-28

Larkins, William D.

Metal treatment

Stock

Ferrous

357 48, 357 89, 357 92, 148175, H01L 2704

Patent

active

045675015

ABSTRACT:
An I.sup.2 L semiconductor device in which a p-type buried layer is formed on an n.sup.+ type silicon substrate by diffusion of boron, an epitaxial n-type layer is grown on the p-type buried layer, a p.sup.+ type region is formed in a ring shape to surround the epitaxial n-type layer with the bottom of the p.sup.+ region reaching to the p-type buried layer, an n-type resistor layer is formed in the epitaxial n-type layer by diffusion of phosphorus, and connections for electrodes are formed by diffusion of n.sup.+ type impurities in such a manner that the connections make contact with the resistor layer.

REFERENCES:
patent: 3575741 (1971-04-01), Murphy
patent: 3865648 (1975-02-01), Castrucci et al.
patent: 3916218 (1975-10-01), Berger et al.
patent: 4087900 (1982-05-01), Yiannoulos
patent: 4101349 (1978-07-01), Roesner et al.
patent: 4106049 (1978-08-01), Shinozaki et al.
patent: 4228450 (1980-10-01), Anantha et al.

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