Method for manufacturing a VDMOS transistor

Details Method for manufacturing a VDMOS transistor Method for manufacturing a VDMOS transistor

1994-08-09

1995-06-13

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 6, 437150, 148DIG126, H01L 218232

Patent

active

054242312

ABSTRACT:
A VDMOS transistor having a reduced drain/source resistance without a corresponding decrease in breakdown voltage and a manufacturing method therefor. Such a VDMOS transistor is created by gradually increasing the doping density of the transistor's implanted regions, while simultaneously increasing the respective thicknesses of the gate oxide layers corresponding to the implanted regions along the current flow path.

REFERENCES:
patent: 4879254 (1989-11-01), Tsuzuki et al.
patent: 4914058 (1990-04-01), Blanchard
patent: 5082795 (1992-01-01), Temple
patent: 5155052 (1992-10-01), Davies
patent: 5171705 (1992-12-01), Choy
patent: 5182222 (1993-01-01), Malhi et al.
patent: 5248627 (1993-09-01), Williams
patent: 5250450 (1993-10-01), Lee et al.

Affiliated with

Also associated with

Rating

Method for manufacturing a VDMOS transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing a VDMOS transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a VDMOS transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1308834