Method of fabricating NMOS and PMOS FET's in a CMOS process

Details Method of fabricating NMOS and PMOS FET's in a CMOS process Method of fabricating NMOS and PMOS FET's in a CMOS process

1994-04-11

1995-06-13

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 57, 437149, 257404, 257369, H01L 21266, H01L 21336, H01L 218238, H01L 218236

Patent

active

054242266

ABSTRACT:
A FET which can be formed on a silicon substrate and which can operate in the enhancement mode. The n+ source and drain are centrally located within n-wells which extend under the gate area, and are separated by a distance. By appropriately choosing the distance between n-wells, different threshold voltages can be obtained for several transistors on the same chip.

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