Test sequence generation method

Details Test sequence generation method Test sequence generation method

1992-09-23

1996-01-09

Voeltz, Emanuel T.

Excavating

371 27, G06F 1127, G06F 11273

Patent

active

054835437

ABSTRACT:
A method for generating a test sequence for a fault in a sequential circuit to provide high fault coverage. In one embodiment (FIG. 1), a circuit state, which a system fails to justify, is stored as an illegal state in a step 107. In a step 103, a target fault is selected. In a step 104, the system performs its fault propagation processing to generate a test sequence and propagate the target fault from a fault location to any external output pin in such a manner that the circuit state does not coincide with the illegal state set stored in the step 107, and judges the success or failure of the sequence generation. In a step 105, the system performs its state initialization processing to generate a test sequence and transfer the state of the circuit from its initial state to a state when the fault was sensitized in such a manner that the circuit state does not coincide with the illegal state set stored in the step 107, and judges the success or failure of the sequence generation. Since the circuit state when the system fails to justify the state is stored as the illegal state so that a circuit state at the time of generating a subsequent test sequence is prevented from coinciding with the illegal state set, the possibility of the successful test sequence generation can be increased and thus the test sequence generation system can achieve high fault coverage.

REFERENCES:
patent: 5189365 (1993-02-01), Ikeda et al.
patent: 5257268 (1993-10-01), Agraveal et al.
Niermann, et al.; "HITEC: A Test Generation Package for Sequential Circuits", published pursuant to a European Design Automation Conference held in 1991. 25-28 Feb.
"Stuck at Fault Testing" of Fault Tolerant Computing Theory and Techniques, vol. I, by Prentice-Hall, Englewood Cliff, N.J.
Schultz, "Essential: An Efficient Self-Learning Test Pattern Generation Algorithm for Sequential Circuits," IEEE International Test Conference, pp. 28-37, Aug. 1989.

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