Method to increase performance in a multi-level cache system by

Details Method to increase performance in a multi-level cache system by Method to increase performance in a multi-level cache system by

1989-07-05

1992-10-13

Popek, Joseph A.

Boots, shoes, and leggings

364DIG1, G06F 1208

Patent

active

051558327

ABSTRACT:
A computing system includes a processor, a system memory containing data utilized by the processor and two cache memories. Each cache memory is connected directly to the processor. A first cache memory is connected to the processor. A second cache memory is connected to the processor and to the system memory. The second cache memory contains a subset of data in the system memory. The first cache memory contains a subset of data in the second cache memory. Data integrity in the system memory is maintained using the second cache memory only. During the execution of a first instruction data required for execution of the first instruction might not be available in the first cache memory. The data required for execution of the first instruction is obtained from the second cache memory and written into the first cache memory. If, however, there is an attempt to access from the first cache memory data required for a second instruction, and this attempt to access the first cache memory occurs simultaneously to the time when the data required for execution of the first instruction is being written from the school cache memory to the first cache memory, then a cache miss is forced and the second cache memory is accessed for the data required for execution of the second instruction.

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