Semiconductor memory having a plurality of banks usable in a plu

Details Semiconductor memory having a plurality of banks usable in a plu Semiconductor memory having a plurality of banks usable in a plu

1994-07-19

1996-01-09

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 365233, G11C 700

Patent

active

054834970

ABSTRACT:
A semiconductor memory having a plurality of banks, a first specify unit, and a second specify unit. The first specify unit is used to specify one of the banks by decoding a bank address signal contained in a row address signal. The second specify unit is used to specify one of the banks by decoding the bank address signal contained in the row address signal, according to bank status signals that indicate whether or not each of the banks is activated. Therefore, the semiconductor memory is used for different bank configurations. Namely, with this arrangement, the semiconductor memory is capable of serving as a memory having a smaller number of banks, to thereby improve convenience.

REFERENCES:
patent: 4987537 (1991-01-01), Kawata
patent: 5043947 (1991-08-01), Oshima et al.
patent: 5251174 (1993-10-01), Hwang
patent: 5355344 (1994-10-01), McClure
K. Cheung et al., "Design and Analysis of a Gracefully Degrading Interleaved Memory System", IEEE Transactions on Computers, vol. 39, pp. 63-71 (1990).

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