Nonvolatile semiconductor memory device having a reduced delay i

Details Nonvolatile semiconductor memory device having a reduced delay i Nonvolatile semiconductor memory device having a reduced delay i

1994-04-07

1996-01-09

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518911, 36518907, 36518909, 36518512, 327 53, 327 56, G11C 1606

Patent

active

054834945

ABSTRACT:
A nonvolatile memory device includes a matrix array of transistors. A read potential generation circuit provides a potential to a selected transistor and generates a read potential in accordance with the flow of current which indicates the data storage state of the transistor. A reference potential generation circuit provides a potential to a selected dummy transistor and generates a reference potential based on the current which flows through the dummy transistor. The memory device incorporates one or more strategies to prevent the relative magnitudes of the read potential and reference potential from being erroneously inverted immediately after the nonvolatile memory is switched from standby to an operational mode. A reference potential decreasing circuit incorporated within the reference potential generation circuit is activated for a predetermined time period after chip enable. Alternatively, a read potential increasing circuit is coupled to the output of the read potential generating circuit and is activated for a predetermined time period after chip enable. Both a reference potential decreasing circuit and a read potential increasing circuit can be included in the nonvolatile memory circuit.

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patent: 5245570 (1993-09-01), Fazio et al.
patent: 5293345 (1994-03-01), Iwahashhi

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