Pipelined apparatus and method for controlled loading of floatin

Details Pipelined apparatus and method for controlled loading of floatin Pipelined apparatus and method for controlled loading of floatin

1991-08-08

1992-10-13

Kriess, Kevin A.

Boots, shoes, and leggings

364DIG1, 3642318, 3642434, 36424311, 364240, 395425, G06F 1300, G06F 1208

Patent

active

051558165

ABSTRACT:
A microprocessor having a pipelined architecture, an onchip data cache, a floating-point unit, a floating-point data latch and an instruction for accessing infrequently used data from an external memory system is disclosed. The instruction comprises a first-in-first-out memory for accumulating data in a pipeline manner, a first circuit means for coupling data from the external bus to the first-in-first-out memory and a second circuit means for transferring the data stored in the first-in-first-out memory to the floating-point data latch. The second circuit means also couples data from the cache to the first-in-first-out memory in the event of a cache hit. Finally, a bus control means is provided for controlling the orderly flow of data in accordance with the architecture of the microprocessor.

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