Static information storage and retrieval – Floating gate – Particular biasing
Patent
1993-11-18
1996-01-09
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular biasing
36518512, 36518529, 36518527, 36518526, G11C 700
Patent
active
054834856
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor system and particularly to a method of erasing a flash (entire array erasure type) EEPROM.
2. Technical Background
FIG. 9 shows a circuit diagram of a flash EEPROM constructed in accordance with the prior art. For simplicity, the flash EEPROM is assumed to be a four-memory-transistor structure. It comprises four memory transistors 1-4, an N-channel transistor 5, a P-channel transistor 6, an X-decoder circuit 118, a write/erase control circuit 119, an interface circuit 23 and an inverter circuit 30. The flash EEPROM also comprises an address buffer 92, a Y-decoder circuit 94, a sense amplifier 96 and a data buffer 98. The EEPROM further comprises bit lines BL1, BL2, word lines WL1, WL2 and a source line SL.
The interface circuit 28 functions to convert a fluctuation of input voltage at Vdd-GND into a fluctuation of output voltage at Vpp-GND.
Address signal is inputted into the X- and Y-decoders 118, 94 through the address buffer 92. Thus, the X-decoder 118 generates X-decode signals for the memory transistors and wordline signals to the word lines WL1 and WL2. On the other hand, the Y-decoder 94 generates Y-decode signals which are in turn supplied to the write/erase control circuit 119 and sense amplifier 96.
The write/erase control circuit 119 is responsive to the Y-decode signal to control the writing of data. More particularly, the write/erase control circuit 119 writes data signals inputted thereinto through the data buffer 98 into the memory transistors 1-4 using the Y-decode signals as addresses. The write/erase control circuit 119 can also erase the data stored in the memory transistor 1-4.
The sense amplifier 96 reads out the data stored in the memory transistors 1-4 using the Y-decode signals as addresses. The read data are then outputted, as data signals, from the sense amplifier 96 to any external unit through the data buffer 98.
The operation of such a prior art system will now be described with reference to FIG. 10 which illustrates the voltages at various different components.
As shown in FIG. 10, the writing to the memory transistor 1 is carried out when WL1 and BL1 are respectively in high-voltage Vpp level and WL2 and BL2 are respectively in GND level. When the erase signal is made L level (lower logical invert level), the N-channel transistor 5 is turned on and the P-channel transistor 6 is turned off. Thus, the source line SL becomes GND level to cause the memory transistor 1 to generate a channel current and also to generate hot electrons at the drain region edge thereof. The electrons are then injected into a floating gate electrode which in turn performs the writing operation. In this case, no writing operation will not be carried out in the other memory transistors 2-4 since no channel current is generated therein.
When the erasing operation is to be performed, as shown in FIG. 10, WL1 and WL2 are made GND level while BL1 and BL2 are made open level. Further, the erase signal is shifted to H level (upper logical invert level) so that the N-channel and P-channel transistors 5, 6 will be turned off and on, respectively. Thus, the source line SL becomes Vpp level so that tunnel current will be generated between the floating gate electrodes and the source region. Electrons are then released from the floating gate electrodes to the source region for erasing.
In the prior art, it is a highly technical problem that in the writing or erasing operation, the threshold voltage in a memory transistor must be limited within a proper range. For example, if the erasure is too much made, the release of electrons is too much made so that the threshold voltage in the memory transistor will be shifted to negative level. Even if only one memory transistor becomes such a depletion type by the overerasing, leak current will flow into a bit line connected to that memory transistor. As a result, it is impossible to read the memory transistor connected to this bit line.
Such a problem may be ov
REFERENCES:
patent: 4797856 (1989-01-01), Lee et al.
patent: 5051953 (1991-09-01), Kitazawa et al.
patent: 5097446 (1992-03-01), Shoji et al.
patent: 5315547 (1994-05-01), Shoji et al.
Le Vu A.
Nelms David C.
Seiko Epson Corporation
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