Method and structure for reducing carry delay for a programmable

Details Method and structure for reducing carry delay for a programmable Method and structure for reducing carry delay for a programmable

1994-04-08

1996-01-09

Mai, Tan V.

Boots, shoes, and leggings

364788, G06F 750

Patent

active

054834783

ABSTRACT:
A carry-lookahead structure for programmable architectures includes a number of M-bit carry lookahead units, each M-bit unit having two parallel programmable carry paths having AND gates controlled by configuration bits to program the beginning and end of an operating carry chain within the M-bit units, as well as the beginning locations in each unit, one path generating a first set of carry bits for the case of the carry-in equal to 0, and the other generating a second set of carry bits for the case of the carry-in equal to 1, and at least one multiplexer controlled by the carry-in for selecting one of the two carries at the most significant bit of the first and second sets of carry bits as carry-out of the unit. Each M-bit unit may further include multiplexers controlled by the carry-in for selecting which of the first and second sets of carry bits are the correct carry bits for addition and M sum logic elements for generating the outputs of sum bits. An alternative is an adder in which the precomputation of the sums is performed for the two possible values of carry-in in each M-bit unit, providing two sets of sum bits, and where multiplexers select which of the two sets of the sum bits is the correct sum and which of the two carry bits produced in the most significant bit of the unit is used as the carry-out of the unit in response to the actual carry-in value of the unit.

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Joseph J. F. Cavanagh, "Digital Computer Arithmetic Design and Implementation", McGraw-Hill Book Company, 1984, pp. 117-122.

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