Boots – shoes – and leggings
Patent
1994-03-04
1996-01-09
Mai, Tan V.
Boots, shoes, and leggings
3647462, 364754, 364760, G06F 752, G06F 700, G06F 1500
Patent
active
054834775
ABSTRACT:
A multiplying circuit wherein an adder 7 outputs a value "0" in which both of a positive part and a negative part of a number with a redundant code are "1", and at a last cycle of the multiplication cycles, the finish detecting circuit 13 detects finishing of multiplication cycles by detecting that "1" exists in a portion storing a positive part of a number with a redundant code of the third bit from the lowest bit of the second latch 8 and in a portion storing a negative part of the same at the same time. In such a construction, a counter circuit for counting multiplication cycles according to the Booth algorithm utilizing a number with a redundant code can be omitted. Accordingly, the number of transistors is reduced and the circuit configuration becomes simple.
REFERENCES:
patent: 4238833 (1980-12-01), Ghest et al.
patent: 4538239 (1985-08-01), Magar
patent: 4644488 (1987-02-01), Nathan
patent: 4868777 (1989-09-01), Nishiyama et al.
patent: 5231415 (1993-07-01), Hagihara
patent: 5365471 (1994-11-01), Sato
"A New Carry-Free Division Algorithm And Its Application To A Single-Chip 1024-b RSA Processor", pp. 748-756, IEEE Journal of Solid-State Circuits, vol. 25, No. 3, Jun. 1990.
Fujita Kouichi
Sato Fumiki
Mai Tan V.
Mitsubishi Denki & Kabushiki Kaisha
Moise Emmanuel L.
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