Routing algorithm method for standard-cell and gate-array integr

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364489, G06F 1750

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active

054834619

ABSTRACT:
An electronic design automation tool embodiment of the present invention comprises a five step process. In a first step, for each pin-master of arbitrary shape in a cell-master a pin access direction is identified, a region in which placing a via will connect a pin to a metal layer, and cause no design rule violation to other pin-masters, is physical bounded on the surface of a chip. Such a region is defined to be a "via-region" of the pin-master. In a second step, at least one "via-spot" within each via-region is identified that violates no design rules if vias are placed at these points. In a third step, vias are placed on each cell instance according to their via-spots. In a fourth step, a "maze-routing" is done to connect the neighboring same net pins by metal-1. In a fifth step, the vias on the pins connected by the maze-router are removed, leaving only one via on a pin if the connection for a current net is not complete.

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"A New Routing Region Definition and Ordering Scheme Using L-Shaped Channels" by Dai et al., IEEE Proceeding of ISCAS 1985, pp. 29-30.
"A Routing Program Applicable to Various Chip Structure of Gate Arrays" by Terai et al, Joho Shori Gakkai Ronbunshi, vol. 25, No. 3, May 1984, pp. 357-364.
"A New Two-Dimensional Routing Algorithm" by Chi-Ping Hsu, IEEE 19th Design Automation Conf., 1982, pp. 46-50.
Takashi, Fujii, et al., "A Multi-Layer Channel Router with New Style of Over-the-Cell Routing," Proceedings of the 29th ACM/IEEE Design Automation Conference, 1992, pp. 585-588.

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