Excavating
Patent
1990-12-26
1992-10-13
Canney, Vincent P.
Excavating
371 221, G01R 3128
Patent
active
051557339
ABSTRACT:
An arrangement is disclosed that is added to digital circuit device for providing a way of easily verifying that the device's input and output circuits are operating and connected properly. The arrangement implements a test mode in which a simple exercising sequence is placed on any single input of a defined sequential group of device pins. A resultant output can be observed on the next occurring output and all subsequent outputs of the defined sequential group.
REFERENCES:
patent: 4975641 (1990-12-01), Tanaka et al.
patent: 4989209 (1991-01-01), Littlebury et al.
AG Communication Systems Corporation
Canney Vincent P.
Hendricks Gregory G.
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