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357 238, 357 234, H01L 2940

Patent

active

051555743

ABSTRACT:
A discrete array (30) of p-type regions (31) surrounding channel regions of n-channel MOSFET cells is provided in a drain region of the MOSFET cells. The p-type regions have depth corresponding to the depth of p-type areas (5) defining the channels. A depletion layer (F1) which is generated and extends from the channel regions through application of a voltage is stretched by the p-type regions, so that the electric field in the depletion layer is weakened. As a result, anti-breakdown ability of the MOSFET cells is improved. The discrete arrangement of the p-type regions is required in order to obtain current path between the channels and n-type drain regions (4).

REFERENCES:
patent: 4574209 (1986-03-01), Lade et al.
patent: 4901127 (1990-02-01), Chow et al.

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