Process of fabricating split gate flash memory cell

Details Process of fabricating split gate flash memory cell Process of fabricating split gate flash memory cell

1995-05-12

1996-01-09

Fourson, George

Fishing, trapping, and vermin destroying

437984, 257316, 257321, H01L 218247

Patent

active

054828791

ABSTRACT:
A process of fabricating a split gate flash memory cell first forms a stacked-gate structure on a face of a substrate. The stacked-gate structure includes a tunnel oxide, a polysilicon floating gate, an inter-poly dielectric and a first polysilicon control gate. A drain region is formed into the substrate at one side of the stacked-gate structure, and is self-aligned with the stacked-gate structure. Thermal oxidation is performed to form sidewall oxides on the sidewalls of the stacked-gate structure, and gate oxide on the substrate. A second polysilicon control gate is deposited over the first polysilicon control gate, sidewall oxides and gate oxide, and is connected with the first polysilicon control gate to form a common control gate. A source region is formed in the substrate at another side of the stacked-gate structure, and is self-aligned with the substantially upright portion of the second polysilicon control gate located at the another side of the stacked-gate structure.

REFERENCES:
patent: 4868629 (1989-09-01), Eitan
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patent: 5427968 (1995-06-01), Hong
Samachisa, Gheorge, et al. (1987) "A 128K Flash EEPROM Using Double-Polysilicon Technology", IEEE J. Sold-State Circuits, vol. SC-22, (5):676-683, Oct. 1987.

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