High density memory array packaging

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

361412, 257723, H01L 2512, H01L 2516, H01L 2312

Patent

active

051914042

ABSTRACT:
A low-profile, high-density package for intergrated circuit chips is provided. A first multichip memory module includes first and second interconnect members having low-profile memory chips mounted on a first side of each member. Low-profile edge clips are employed to mechanically connect a second side of the second member to a second side of the first member, and to electrically connect the first sides of the members to a first surface of a circuit board. Likewise, a second multichip memory module includes first and second interconnect members having low-profile memory chips mounted to a first side of each member. Low-profile edge clips are employed to mechanically connect the second sides of the members, and to electrically connect the first sides of the members to a second surface of the circuit board. A thermal management technique that distributes thermal loads is thereafter applied to create a high-density package capable of insertion into a standard computer backplane and cabinet.

REFERENCES:
patent: 3414892 (1968-12-01), McCormack et al.
patent: 3588852 (1971-06-01), McCormack et al.
patent: 3614541 (1971-10-01), Farrand
patent: 3676926 (1972-07-01), Kendall
patent: 3769679 (1973-11-01), Kendall
patent: 3805117 (1974-04-01), Hausman
patent: 3877064 (1975-04-01), Scheingold et al.
patent: 4009485 (1977-02-01), Koenig
patent: 4059849 (1977-11-01), Mitchell
patent: 4283755 (1981-08-01), Tracy
patent: 4316321 (1982-02-01), Wichham
patent: 4365284 (1982-12-01), Tanaka et al.
patent: 4481559 (1984-11-01), Buck et al.
patent: 4578697 (1986-03-01), Takemae
patent: 4592617 (1986-06-01), Seidler
patent: 4638348 (1987-01-01), Brown et al.
patent: 4640499 (1987-02-01), Hemler et al.
patent: 4647126 (1987-03-01), Sobota, Jr.
patent: 4647126 (1987-03-01), Sobota, Jr.
patent: 4688150 (1987-08-01), Peterson
patent: 4703393 (1987-10-01), Yamamoto et al.
patent: 4730238 (1988-03-01), Cook
patent: 4763188 (1988-08-01), Johnson
patent: 4766478 (1988-08-01), Dennis
patent: 4771366 (1988-09-01), Blake et al.
patent: 4782589 (1988-11-01), Dennis
patent: 4827611 (1989-05-01), Pai et al.
patent: 4882657 (1989-11-01), Braun
patent: 4894749 (1990-01-01), Elko et al.
"Clipped Decoupled Twin-Carrier Module for IC Memory Chips"-Hinrichsmeyer et al.-IBM Technical Disclosure Bulletin vol. 27, No. 8-Jan. 1985.
IBM Technical Disclosure Bulletin, vol. 27, No. 8, Jan. 1985, pp. 4857-4858.
IBM Technical Disclosure Bulletin, vol. 28, No. 10, Mar. 1986 pp. 4360-4361, N.Y., "Surface mount substrate lead".
IBM Technical Disclosure Bulletin, vol. 22, No. 2, Jul. 1979, pp. 573-574, N.Y., B. T. Clark, "Thermal Enhancement of Integrated Stacked Modules".
Fujitsu Scientific & Technical Journal, vol. 21, No. 4, Sept. 1985, pp. 452-460, N.Y., M. Takamura et al., "High-Density packaging main of storage".
35th ECC, Washington, DC, 20th-22nd May 1985, IEEE 0569-5503/85/0000-0512, pp. 512-516, IEEE, N.Y., I. Munakata et al., "An advanced multi-layer technology in thick film hybrid circuits".
Article entitled "A New Face Down Bonding Technique Using a Low Melting Point Metal" by Miki Mori, Masayuki Saito, Akinori Hongu, Akira Miitsuma, and Hiroshi Ohdaira, from "Proceedings of 1989 Japan International Electronic Manufacturing Technology Symposium", Apr. 1989 at pp. 114-118.
Article entitled, "High-Density, Large Scale Interconnection For Improved VLSI System Performance" by W. J. Bertram, Jr. from Technical Digest, 1987 International Electron Devices Meeting, Dec. 1987 at pp. 100-103.
Article entitled, "High-Accuracy Inner Lead Bonding Technique" by Yukihiro Ikeya, Koichiro Atsumi, Noriyasu Kashima, Yoichiro Maehara, Keitaro Okano, from Proceedings of 1989 Japan International Electronic Manufacturing Technology Symposium, Apr. 1989 at pp. 71-74.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

High density memory array packaging does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High density memory array packaging, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High density memory array packaging will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-130090

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.