Fabrication method of a semiconductor device having a planarized

Details Fabrication method of a semiconductor device having a planarized Fabrication method of a semiconductor device having a planarized

1991-06-10

1992-10-13

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437228, 437195, H01L 2144

Patent

active

051550644

ABSTRACT:
A semiconductor device having a multi-level interconnection structure includes an active device, a substrate supporting the active device thereon, and a first insulator layer provided so as to cover the substrate including the active device. A first conductor pattern is provided on the first insulator layer. A planarizing layer has a planarized top surface provided on the first insulator layer so as to bury the first conductor pattern underneath. A second insulator layer is provided on the planarized top surface of the planarizing layer. A contact hole is provided on the second insulator layer so as to expose a desired part of the first conductor pattern. A second conductor pattern is provided on the second insulator layer in correspondence to the contact hole so as to fill the contact hole and so as to make a contact to the exposed part of the first conductor pattern. An isolated region is provided on the substrate in correspondence to a part of the substrate underneath the contact hole such that the isolated region is projected from the first top surface of the substrate in correspondence to the contact hole. The isolated region causes a projection of the top surface of the first insulator layer in correspondence to a part which covers the isolated region such that the planarizing layer provided on the first insulator layer is eliminated from the part of the first insulator having the projecting top surface.

REFERENCES:
patent: 4369565 (1983-01-01), Muramatsu
patent: 4470062 (1984-09-01), Muramatsu
patent: 4676867 (1987-06-01), Elkins et al.
patent: 4789648 (1988-12-01), Chow et al.
patent: 4853343 (1989-08-01), Uchida et al.
patent: 4920070 (1990-04-01), Mukai
patent: 4920072 (1990-04-01), Keller et al.

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