Vertical field effect transistor with improved control of low re

Details Vertical field effect transistor with improved control of low re Vertical field effect transistor with improved control of low re

1991-06-14

1992-10-13

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 26, 437 27, 437 28, 437 29, 437 41, H01L 21265

Patent

active

051550520

ABSTRACT:
A method for making a vertical field effect transistor with improved commutating safe operating area is provided a sidewall spacer is formed around a polysilicon gate, and used as a mask for the formation of a low resistivity region. The low resistivity region is formed underneath a source region and extends laterally to within a few thousand angstroms of the lateral boundary of the source region. A central portion of the source region is subsequently removed exposing a portion of the underlying low resistivity region and a source electrode is formed in contact with the exposed low resistivity region and the source region.

REFERENCES:
patent: 4748103 (1988-05-01), Hollinger
patent: 4774198 (1988-09-01), Contiero et al.
patent: 4809047 (1989-02-01), Temple
patent: 4879254 (1989-11-01), Tsuzuki et al.
patent: 4895810 (1990-01-01), Meyer et al.
patent: 4960723 (1990-10-01), Davies
patent: 4970173 (1990-11-01), Robb
patent: 5118638 (1992-06-01), Fujihira
Mori et al., "An Insulated Gate Bipolar Transistor with a Self-Aligned DMOS Structure", IEEE IEDM, 1988, pp. 813-816.

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