Data-processing system with a set of peripheral units repetitive

Details Data-processing system with a set of peripheral units repetitive Data-processing system with a set of peripheral units repetitive

1976-11-01

1978-06-13

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 916

Patent

active

040952665

ABSTRACT:
A multiplicity of peripheral units are consecutively scanned, in respective phases of a recurrent operating cycle, by a central unit including a processor for incoming and outgoing data. The processor is connected to a programmer emitting a series of binary instructions during each phase, the instructions being stored in a read-only memory from which they are read out during respective subphases of each phase under the control of an address counter, the last instruction of a series carrying a characteristic bit which advances a phase counter and causes a switch of the central unit to a different peripheral unit. At the beginning of each new phase, the address counter receives an initial count from a random-access memory addressed by the phase counter, this initial count representing the address of the first instruction of the series to be executed in that phase; the initial count is entered in a corresponding stage of the random-access memory, in response to the characteristic phase-changing bit, for subsequent readout in a homologous phase of the next operating cycle. The address counter includes an incrementer progressively increasing its count at the end of each subphase; upon the appearance of a special instruction in the output of the read-only memory, initiating a microprogram including one or more ancillary instructions, the reading of the address counter identifying that special instruction is stored in a buffer register and, after incrementation, is fed back to the address counter to restart its count with the address immediately following the one of the special instruction. In response to a malfunction within the system, the processor loads the phase counter with the address of an extracurricular phase used for testing operations and not assigned to any peripheral unit.

REFERENCES:
patent: 3518632 (1970-06-01), Threadgold et al.
patent: 3656123 (1972-04-01), Carnevale et al.
patent: 3997896 (1976-12-01), Cassarino, Jr. et al.

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