1979-08-10
1981-12-01
Larkins, William D.
357 35, 357 86, H01L 2704, H01L 2972
Patent
active
043039324
ABSTRACT:
For the sake of an increased operational security and a reduction of substrate currents of an intergrated semiconductor circuit with a lateral transistor and a pn insulation, a protective zone exhibiting the opposite conductivity type and contacted barrier-free together with the collector of the collector electrode is inventively provided in the collector of the lateral transistor.
REFERENCES:
patent: 3590345 (1971-06-01), Brewer
patent: 3676714 (1972-07-01), Wensink et al.
patent: 3878551 (1975-04-01), Callahan Jr.
patent: 4070654 (1978-01-01), Tachi
patent: 4117507 (1978-09-01), Pacor
patent: 4156246 (1979-05-01), Pedersen
Lehning, IEEE J. of Solid State Circuits, vol. SC 9 No. 5 Oct. 1974, pp. 228-229.
Hamilton and Howard, Basic Integrated Circuit Engineering, (McGraw-Hill, NY 1975) p. 7.
Warner Jr. et al., "Bipolar Lock-layer Transistor," Solid-State Electronics, (Pergammon Press, London) vol. 18, 1975, p. 323.
Larkins William D.
Siemens Aktiengesellschaft
LandOfFree
Lateral transistor free of parisitics does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Lateral transistor free of parisitics, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Lateral transistor free of parisitics will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1299475