Two's complement multiplier circuit

Details Two's complement multiplier circuit Two's complement multiplier circuit

1982-09-24

1985-03-26

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

045077495

ABSTRACT:
A multiplication circuit includes a multiplying unit for multiplying a signed multiplier X represented in terms of the two's complement of n bits by a signed multiplicand Y represented in terms of two's complement of n bits to generate a signed multiplication output data of (2n-1) bits represented in terms of the two's complement, an exclusive-OR circuit for producing the exclusive-OR of the sign bits X.sub.S and Y.sub.S of the respective values X and Y, and a selecting circuit for generating a sign bit "0" when the most significant bit of the multiplication output data from the multiplying unit is "0" and generating as a sign bit an output bit of the exclusive-OR circuit when the most significant bit is "1".

REFERENCES:
patent: 3866030 (1975-02-01), Baugh et al.
patent: 4086474 (1978-04-01), Negi et al.
Robertson, "Two's Complement Multiplication in Binary Parallel Digital Computers", IRE Trans.-Electronic Computers, Sep. 1955, pp. 118-119.
Dauby et al, "Two's Complement Multiplier", IBM Tech. Disclosure Bulletin, vol. 18, No. 5, Oct. 1975, pp. 1482-1483.
Capps et al, "Two's-Complement Multiplication", IBM Tech. Disclosure Bulletin, vol. 20, No. 12, May 1978, pp. 5292-5293.

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