Structure and method for issuing interrupt requests as addresses

Details Structure and method for issuing interrupt requests as addresses Structure and method for issuing interrupt requests as addresses

1997-10-28

1998-09-08

Pan, Daniel H.

395741, 395829, G06F 1206, G06F 1324, G06F 1310

Patent

active

058059024

ABSTRACT:
An interrupt control circuit for use in a computer system has a CPU, a peripheral I/O device, and a bus having address lines for carrying signals to and from the peripheral I/O device. Interrupt requests generated by the I/O device are encoded as address signals which are transmitted on the address bus lines. A predetermined set of addresses are set aside to represent the interrupt requests. The interrupt control circuit is coupled to the address bus lines to receive the encoded interrupt requests. The interrupt control circuit has an address decoder which receives address signals from the I/O device. When these address signals represent an address within the predetermined set of addresses set aside to represent the interrupt requests, the address decoder uses the address signals to create a plurality of interrupt control signals. The interrupt control signals are provided to an interrupt latch/decoder which uses the interrupt control signals to create interrupt request signals. The interrupt request signals are provided to an interrupt controller. In response, the interrupt controller and the CPU process the interrupt request.

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MCS--80/85 Family User's Manual; pp. 2-3, 2-4; Fig. 2-3; Intel Corporation, CA 1986.

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