In a pipelined processor, setting a segment access indicator dur

Details In a pipelined processor, setting a segment access indicator dur In a pipelined processor, setting a segment access indicator dur

1996-02-23

1998-09-08

Lall, Parshotam S.

395568, G06F 934, G06F 938

Patent

active

058058796

ABSTRACT:
In a pipelined processor having at least one execution pipeline for executing instructions, the execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages, the processor capable of addressing segments of system memory coupled thereto, a circuit for, and method of, setting a segment access indicator associated with a segment of the system memory being accessed by the processor. The circuit includes: (a) exception generating circuitry to generate an exception when the segment access indicator requires setting and (b) exception handling circuitry, invoked by the processor in response to generation of the exception, to flush the execution pipeline of instructions following a segment load instruction, set the segment access indicator and load an address pointer of the processor with an address corresponding to a specified location within the segment.

REFERENCES:
patent: 5144551 (1992-09-01), Cepulis
patent: 5255379 (1993-10-01), Melo
patent: 5517651 (1996-05-01), Huck et al.
patent: 5537559 (1996-07-01), Kane et al.
patent: 5596755 (1997-01-01), Pletcher et al.

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