Patent
1995-09-08
1998-09-08
Butler, Dennis M.
395558, 395559, G06F 104
Patent
active
058058729
ABSTRACT:
A computer system including a cache which has a wave pipeline read controller is described. The system in addition to the cache memory includes a processor coupled to the cache memory. The processor includes a register stack which stores values corresponding to a wave number and read speed which is loaded as part of a configuration of the processor. The processor determines a repetition rate for read data corresponding to a difference between the values of read speed and wave number. The processor includes a logic delay line comprised of a plurality of clock delay elements, each of said elements providing successively increasing discrete delays to a clock signal fed to the logic delay line. The delay line is used to provide inputs to a first and second multiplexer which are respectively controlled by a signal corresponding to a desired repetition rate for read cycles and a signal corresponding to the read speed of the cache memory. The delay pipeline permits address cycles to initiated earlier increasing data read bandwidth while reducing data valid windows.
REFERENCES:
patent: 5239639 (1993-08-01), Fischer et al.
patent: 5335337 (1994-08-01), Gaglairdo et al.
patent: 5469547 (1995-11-01), Pawlowski
patent: 5557781 (1996-09-01), Stones et al.
patent: 5615358 (1997-03-01), Vogley
Butler Dennis M.
Digital Equipment Corporation
Hudgens Ronald C.
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