Parallel processor performing bypass control by grasping portion

Details Parallel processor performing bypass control by grasping portion Parallel processor performing bypass control by grasping portion

1996-11-07

1998-09-08

Donaghue, Larry D.

39580023, 39580024, G06F 1516

Patent

active

058058524

ABSTRACT:
A bypass control circuit uses a plurality of entries corresponding to a plurality of addresses of a register file to grasp in which one of eight result buffers a processing result of an instruction having a destination address corresponding to any of the plurality of entries exists. When a source address of data to be required by a latch circuit matches with a destination address of a processing result of an instruction held in any of the eight result buffers, the processing result of the instruction having the matching destination address is transferred from a result buffer holding the processing result of the instruction to the latch circuit. Thus, fast bypass control can be achieved.

REFERENCES:
patent: 5313551 (1994-05-01), Labrousee et al.
patent: 5511172 (1996-04-01), Kimura et al.
patent: 5574939 (1996-11-01), Keckler et al.
patent: 5636353 (1997-06-01), Ikenaga et al.

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