Method of operating enhanced alu test hardware

Details Method of operating enhanced alu test hardware Method of operating enhanced alu test hardware

1983-09-29

1986-10-21

Harkcom, Gary V.

Excavating

371 16, 324 73AT, G06F 1100

Patent

active

046189564

ABSTRACT:
Method and hardware associated with an arithmetic logic unit (ALU) in a central processing unit of a data processor provides for testing the inputs to the ALU to see if logical AND is zero or the two inputs are equal while allowing the ALU to perform another function at the time these tests are made.

REFERENCES:
patent: 3614608 (1971-10-01), Giedd et al.
patent: 3931505 (1976-01-01), Sevcik
patent: 3988670 (1976-10-01), Gariazzo
patent: 4286176 (1981-08-01), Oka et al.
patent: 4369511 (1983-01-01), Kimura et al.
DiPilato et al., "Error Detection in Registers where Parity Checking is Unavailable", IBM Technical Disclosure Bulletin, vol. 19, No. 3, Aug. 1976, p. 921.
Davis et al., "Auto-Test CPU Interface", IBM Technical Disclosure Bulletin, vol. 13, No. 11, Apr. 1971, pp. 3583-3584.

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