Memory delay start apparatus for a queued memory controller

Details Memory delay start apparatus for a queued memory controller Memory delay start apparatus for a queued memory controller

1981-03-23

1983-10-18

Nusbaum, Mark E.

Boots, shoes, and leggings

G06F 1306, G06F 1300

Patent

active

044109431

ABSTRACT:
A memory controller couples to a bus and controls a number of memory module units or memory modules. The controller includes a number of queue circuits for processing a variety of different types of memory requests received from a number of command generating units coupled to the bus requiring the controller to operate in a corresponding number of different modes. The controller includes queue start timing control apparatus which couples to the modules and to the queue circuits for resolving conflicts between the types of requests and the internal operations required to be performed by the controller within a minimum of time.

REFERENCES:
patent: 3643227 (1972-02-01), Smith et al.
patent: 3699530 (1972-10-01), Capowski et al.
patent: 4115851 (1978-09-01), Nagano et al.
patent: 4121286 (1978-10-01), Venton et al.
patent: 4214305 (1980-07-01), Tokita et al.
patent: 4228500 (1980-10-01), Webster

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