Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1985-01-28
1986-10-21
Anagnos, Larry N.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307452, 365230, H03K 19096, H03K 1920, H03K 19017, G11C 800
Patent
active
046187847
ABSTRACT:
A decoder/driver circuit for a semiconductor momory having a A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A .PHI.PC line is included for receiving a .PHI.PC precharge clock signal thereon and a .PHI.R line is provided for receiving a .PHI.R reset clock signal thereon. The decoder/driver circuit includes a NOR decoder means having a plurality of transistor switching devices connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on a decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices connected to the output node of the decoder to produce a first selection signal when the decoder output node and the AN line is high and a second selection signal when the decoder output node and the AN line is high. A driver circuit is connected to the selection means and is responsive to the output signal of the NOR decoder circuit and the first selection signal to provide an output signal on a first memory word line and is further responsive to the output signal of the NOR decoder circuit and the second selection signal to provide an output signal on a second memory word line.
REFERENCES:
patent: 4156938 (1979-05-01), Proebsting et al.
patent: 4194130 (1980-03-01), Moench
patent: 4200917 (1980-04-01), Moench
patent: 4259731 (1981-03-01), Moench
patent: 4264828 (1981-04-01), Perlegos et al.
patent: 4301535 (1981-11-01), McKenny
patent: 4309629 (1982-01-01), Kamuro
patent: 4344005 (1982-08-01), Stewart et al.
patent: 4401903 (1983-08-01), Iizuka
patent: 4429374 (1984-01-01), Tanimura
patent: 4433257 (1984-02-01), Kinoshita
patent: 4467225 (1984-08-01), Tanaka
patent: 4471240 (1984-09-01), Novosel
patent: 4477739 (1984-10-01), Proebsting et al.
patent: 4477884 (1984-10-01), Iwahashi
patent: 4514829 (1985-04-01), Chao
patent: 4538247 (1985-08-01), Venkateswaran
IBM Technical Disclosure Bulletin, vol. 25, No. 4, Sep. 1982, pp. 2135-2136, entitled "CMOS Decoder Circuit", by L. M. Terman.
IBM Technical Disclosure Bulletin, vol. 18, No. 12, May 1976, pp. 3955-3966, entitled "High-Speed FET Decoder", by G. H. Parikh.
Chappell Barbara A.
Rajeevakumar Thekkemadathil V.
Schuster Stanley E.
Terman Lewis M.
Anagnos Larry N.
Goodwin John J.
International Business Machines - Corporation
LandOfFree
High-performance, high-density CMOS decoder/driver circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High-performance, high-density CMOS decoder/driver circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-performance, high-density CMOS decoder/driver circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1291597