Switching device for digital data networks and asynchronous tran

Details Switching device for digital data networks and asynchronous tran Switching device for digital data networks and asynchronous tran

1995-07-11

1998-09-08

Hsu, Alpus H.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370415, 370503, H04Q 1104

Patent

active

058055908

ABSTRACT:
In an ATM switch, the total required buffer storage is concentrated in a central memory which is used by all input and output channels. The connection between the input and output channels and the memory is established by a synchronous bus. The time allocation on the bus is designed in such a manner that within the transmitting time of a data cell according to the ATM norm, e.g., over a wide band network, a time slice which is sufficient for the transfer of a complete data cell between an input or an output and the memory is allocated to each input and output. The memory is fixedly divided into areas of the same size, each of the areas serving as a buffer for a respective input. Due to the simple time allocation of the bus it is possible to combine a plurality of input and output channels in an input/output unit and to still realize the latter in a small number of integrated circuits. For the memory, unexpensive standard memory devices can be used.

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