Interruption control system in a multiprocessing system

Details Interruption control system in a multiprocessing system Interruption control system in a multiprocessing system

1978-01-05

1979-07-24

Chapnick, Melvin B.

Boots, shoes, and leggings

G06F 918, G06F 1300

Patent

active

041625293

ABSTRACT:
An entry requirement control system in a multiprocessing system having a plurality of central processing units (CPU's), a common main memory for storing a plurality of programs which are accessed by the CPU's, and a key register provided between the CPU's and the common main memory. A flag bit circuit is incorporated into the system in the form of hardware in the key register and is adapted, upon completion of the execution of a program by one CPU, to only give priority to the earliest entry requirement made by a plurality of CPU's to the same program and prohibit the other CPU's from being given any priority. A flag bit circuit corresponding to each program acts, while one program is executed by one CPU, to prohibit an entry requirement from the other CPU's.

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D. L. Dosch et al., "Multiple Device-Processor Interface" in IBM Technical Disclosure Bulletin, vol. 16, No. 3, Aug. 1973, pp. 887-888.

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