Process for and structure of high density VLSI circuits, having

Details Process for and structure of high density VLSI circuits, having Process for and structure of high density VLSI circuits, having

1982-07-12

1985-03-26

Saba, William G.

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29578, 29591, 148 15, 148187, 148188, 156643, 156653, 156657, 357 239, 357 41, 357 45, 357 59, H01L 21225, H01L 21441

Patent

active

045064377

ABSTRACT:
A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of desired portions only of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability.

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patent: 4210993 (1980-07-01), Sunami
patent: 4221044 (1980-09-01), Godejahn et al.
patent: 4221045 (1980-09-01), Godejahn
Tanigaki et al., "New Self-Aligned Contact Technology" J. Electrochem. Soc., vol. 125, No. 2, Mar. 1978, pp. 471-472.

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