Charge transfer device output

Details Charge transfer device output Charge transfer device output

1992-07-10

1993-03-30

Munson, Gene M.

Electrical pulse counters, pulse dividers, or shift registers: c

Charge transfer device

Particular input or output means

257239, G11C 1928, H01L 2978

Patent

active

051990539

ABSTRACT:
In a CCD element, the influence of a parasitic capacitance existing between a floating diffusion region and a reset gate section of an output section is suppressed to increase sensitivity. In a CCD element in which a floating diffusion region (7) is connected to the final stage of a charge transfer register (1) having a CCD structure through a horizontal output gate section (5) and a reset gate section (11) is disposed between the floating diffusion region (7) and a reset drain region (10), an output gate pulse (.phi..sub.HOG) having an anti-phase of a reset pulse (.phi..sub.RG) applied to the reset gate section (11) is applied to the horizontal output gate section (5). Further, an output waveform in a signal period in a CCD linear sensor can be made flat and a signal level difference between odd-numbered and even-numbered pixels can be improved. In a CCD linear sensor comprising a photo sensing region formed of a plurality of photo sensing elements (pixels), first and second horizontal transfer registers disposed at both sides of the photo sensing region through read-out gate sections, a floating diffusion region for alternately detecting signal charges transferred thereto from the first and second horizontal transfer registers as output signals and a reset gate section, a transfer section of the final stage portion of the first and second horizontal transfer registers is separated and phases of drive pulses (.phi.H.sub.1 '), (.phi.H.sub.2 ') applied to the transfer section of the final stage portion are shifted from those of drive pulses (.phi.H.sub.1), (.phi.H.sub.2) applied to the preceding transfer section, whereby a noise component (36) is superimposed upon the output waveform of ON period (T.sub.R) of the reset gate section.

REFERENCES:
patent: 4092549 (1978-05-01), Prince
patent: 4811371 (1989-03-01), Tower
patent: 4974240 (1990-11-01), Suzuki et al.
patent: 5073908 (1991-12-01), Cazaux

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