Method of forming non-volatile EPROM and EEPROM with increased e

Details Method of forming non-volatile EPROM and EEPROM with increased e Method of forming non-volatile EPROM and EEPROM with increased e

1980-09-08

1983-10-18

Andrews, M. J.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 29578, 29591, 148 15, 148187, 357 23, H01L 21283, H01L 2131

Patent

active

044097239

ABSTRACT:
The floating gate in an N channel EPROM cell extends over the drain diffusion and over a portion of the channel thereby to form a "drain" capacitance between the drain and the floating gate and a "channel" capacitance between the channel and the floating gate. A control gate overlaps the floating gate and extends over the remainder of the channel near the source diffusion thereby to form a "control" capacitance between the channel and the control gate. These three capacitances form the coupling for driving each cell. The inversion region in the channel directly under the control gate is established directly by a "write or read access" voltage applied to the control gate. The inversion region in the channel directly under the floating gate is established indirectly through the drain and control capacitances and the channel capacitance by the control gate voltage and by another write access voltage applied to the drain. In effect, the drain voltage is coupled to the portion of the channel adjacent to the drain through the series driving circuit formed by the drain capacitance and the channel capacitance. During write, hot electrons from the write channel current are directed toward and injected into the floating gate by the transverse electric field between the floating gate and the underlying channel. Stored injection charge on the floating gate raises the conduction threshold of the programmed cell, causing the cell to remain nonconductive during read when standard ("low") access voltages are applied to the control gate. An unprogrammed cell conducts in response to the low read voltages applied to its control gate and drain drive circuit. A cell is erased either by ultraviolet illumination or by electrons from the floating gate tunneling through a region of thinned oxide. The non-symmetrical arrangement of the control gate and floating gate with respect to source and drain allows a very dense array implementation.

REFERENCES:
patent: 4267632 (1981-05-01), Shappir
patent: 4342099 (1982-07-01), Kuo

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