Dynamic shift register cell

Details Dynamic shift register cell Dynamic shift register cell

1975-11-13

1977-04-12

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307208, 307246, 307279, G11C 1928, G11C 1918, H03K 2326, H03K 1760

Patent

active

040177416

ABSTRACT:
A CMOS shift register cell comprising four transistors and two capacitance elements. Data is temporarily stored in the cell by precharging one capacitance through one of the transistors and then discharging it or not through another of the transistors depending on the input signal level. The second capacitance may be precharged through the third transistor and then discharged or not through the fourth transistor, depending upon the value of the temporarily stored charge.

REFERENCES:
patent: 3524077 (1970-08-01), Kaufman
patent: 3651342 (1972-03-01), Dingwall
patent: 3838293 (1974-09-01), Shah
patent: 3866186 (1975-02-01), Suzuki
Cordard et al., "High-Density/High-Performance Two-Phase Shift Register Cell"; IBM Tech. Discl. Bull.; vol. 16, No. 3, pp. 1012-1013, 8/1973.
Reynolds et al., "Metal-Oxide-Semiconductor (MOS) Integrated Circuits"; Post. Off. Electrical Engrs. J. (Gt. Brit.), vol. 63, pt. 2 (7/19700); pp. 105-112.
Parrish et al., "Four-Phase High-Speed Shift Register"; IBM Tech. Discl. Bull.; vol. 13, No. 1, pp. 23-24, 6/1970.

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