Memory access control circuit

Details Memory access control circuit Memory access control circuit

1986-12-11

1989-06-13

Shaw, Gareth D.

Boots, shoes, and leggings

364957, 3649571, 364959, G06F 1206

Patent

active

048398560

ABSTRACT:
Memory address signals consisting of upper and lower address signals output from a memory access circuit are retained by an address counter. An address comparator compares the upper address signal retained by the address counter and the next upper address signal from the memory access circuit. If these upper address signals coincide with each other, a multiplexer is controlled by a timing control circuit, and only the lower address signal held by the address counter is supplied to a memory via an address bus. However, if the above upper address signals do not coincide with each other, the multiplexer is controlled by the timing control circuit. In this case, the upper and lower address signals retained by the address counter are multiplexed, and the multiplexed signals are supplied to the memory via the address bus. The timing control circuit also supplies a row address strobe signal and a column address strobe signal to the memory.

REFERENCES:
patent: 4495565 (1985-01-01), Thompson
patent: 4546451 (1985-10-01), Bruce
patent: 4581721 (1986-04-01), Gunawardana
patent: 4701843 (1987-10-01), Cohen

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