Reduced primary crystalline defect damage in NMOSFETS with an op

Details Reduced primary crystalline defect damage in NMOSFETS with an op Reduced primary crystalline defect damage in NMOSFETS with an op

1996-04-01

1998-09-08

Dang, Trung

Fishing, trapping, and vermin destroying

437 41, H01L 21336

Patent

active

058044558

ABSTRACT:
A method for forming a MOSFET device, having Lightly Doped Drain structures with reduced primary crystalline defect damage wherein a semiconductor structure is provided having a thin silicon oxide layer on a silicon substrate, a polysilicon layer formed on the silicon oxide layer, and a photoresist mask formed on the polysilicon layer. The mask is patterned to form two narrow slit openings through which the polysilicon layer is exposed. The exposed polysilicon is anisotropically etched to define a gate region between the two slits. A first ion implantation forms two lightly doped regions in the substrate on either side of the gate region. The ion implantation takes place through the slits so that the implanted regions in the substrate are narrow. This limits the region of the substrate in which there is primary crystalline defect damage. The first photoresist mask layer is removed. A second photoresist mask layer is formed on all exposed surface areas and patterned so that only the polysilicon gate region is covered. The exposed polysilicon is anisotropically etched and the remaining mask layer is removed. A layer of silicon oxide is deposited on all exposed surface areas. Anisotropic etching is used on the silicon oxide until the substrate not under the polysilicon layer is exposed. Thus, residues of silicon oxide remain on the vertical edges of the gate region to act as spacers. A second ion implantation is performed on both sides of the gate region to form heavily doped regions.

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S. Wolf, R.N. Tauber, Silicon Processing for the VLSI Era, Lattice Press, pp. 295-308, 1996.

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