Package structure for semiconductor device

Details Package structure for semiconductor device Package structure for semiconductor device

1988-02-17

1989-06-13

James, Andrew J.

357 72, 357 74, H01L 2900, H01R 4302

Patent

active

048397130

ABSTRACT:
A package structure comprising a metallic cap having a bottom wall to which the bottom surface of the semiconductor chip is electrically and mechanically connected, a side wall extending from said bottom wall and surrounding the semiconductor chip, and a flange extending outwardly from said side wall substantially parallel to said bottom wall, said flange supporting the lead conductors thereon through an electrically insulating material. The electrical connection means is disposed between the metallic cap flange and the lead conductor for establishing an electrical connection therebetween. The electrical connection means may comprise an electrically conductive projection formed on the flange of the metal cap, extending through a notch in the insulating material and electrically connected to the lead conductor. The electrical connection means may be an electrically conductive bonding material filled within a cavity defined by an opening in the flange of the metal cap, a through hole in the insulating material and a connecting pad of the lead conductor.

REFERENCES:
patent: 4330790 (1982-05-01), Burns
patent: 4649415 (1987-03-01), Hebert

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