Process of fabricating elevated source/drain transistor

Details Process of fabricating elevated source/drain transistor Process of fabricating elevated source/drain transistor

1990-12-10

1993-03-30

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 89, 437192, 257900, 257384, H01L 21265

Patent

active

051983788

ABSTRACT:
An elevated transistor is provided having minimized junctions (33) and a polysilicon pad (27) over the transistor insulating regions (12) and partially over the moat (14). A conductive layer (32) overlays the polysilicon pad (27) and partially overlays the moat (14) in the interim areas (29).

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El-Diwany et al., "Use of the Polysilicon . . . LDD Structures", IEEE, vol. 35, No. 9, Sep. 1988.
Wong et al., "Elevated Source/Drain MOSFET", IEDM, 1984.

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