Method of making biCMOS integrated circuit with shallow N-wells

Details Method of making biCMOS integrated circuit with shallow N-wells Method of making biCMOS integrated circuit with shallow N-wells

1991-10-28

1993-03-30

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 43, 437 59, 437 61, 148DIG9, H01L 21265

Patent

active

051983745

ABSTRACT:
A biCMOS integrated circuit is created on a p-type semiconductor substrate on which first an n-type epitaxial layer then a p-type epitaxial layer is grown. NPN and PMOS transistors are formed in n-wells in the p-type epitaxial layer. n.sup.+ buried layers are located below the n-wells at the interface between the substrate and the n-type epitaxial layer. The n.sup.+ buried layers underlying the n-wells containing NPN transistors are surrounded by p.sup.+ buried layers that extend from the interface between the p-type and n-type epitaxial layers through the n-type epitaxial layers and into the substrate.

REFERENCES:
patent: 4637125 (1987-01-01), Iwasaki et al.
patent: 4957874 (1990-09-01), Soejima
patent: 4960726 (1990-10-01), Lechaton et al.
patent: 5015594 (1991-05-01), Chu et al.
patent: 5141881 (1992-08-01), Takeda et al.

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