Turn-off-processor between keystrokes

Details Turn-off-processor between keystrokes Turn-off-processor between keystrokes

1979-12-26

1983-10-11

Chin, Gary

Boots, shoes, and leggings

364900, G06F 104

Patent

active

044096658

ABSTRACT:
A calculator having constant memory utilizing a classical CMOS metal gate process, a low power microcomputer with on-chip and external constant memory capability, and multiple partition power control of circuit groups. Incorporation of a first and second switched negative voltage and a non-switched negative voltage to the appropriate P (-) wells enables the power hungry clocked logic and the display interface and keystroke detect circuitry, to be turned off while power is maintained on the internal static RAM, and on the RAM write logic, digit latches, and R-lines which connect to both the internal and external RAM, or to selectively connect in combination the first and second switched voltages. In an alternate embodiment, a multiple oscillator, multiple partition system is controlled to provide an off-mode, display only mode (low frequency oscillator), a process only mode, and a display and process mode, thereby optimizing power dissipation to system requirements. In yet another embodiment, the clocked CMOS logic of the system is forced to a designer predefined output logic level in the inactive power down mode. Thus, semi-non-volatile memory (constant memory) capability, power down standby, and display only, capabilities may be achieved. Power consumption less than conventional CMOS is obtainable.

REFERENCES:
patent: 3453601 (1969-07-01), Bogert et al.
patent: 3535560 (1970-10-01), Cliff
patent: 3771132 (1973-11-01), Biewer
patent: 3941989 (1976-03-01), McLaughlin et al.
patent: 4171539 (1979-10-01), Tawfik
patent: 4204249 (1980-05-01), Dye et al.
patent: 4218876 (1980-08-01), Hashimoto et al.
patent: 4271404 (1981-06-01), Tanaka

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