Parallel binary adder having grouped stages including dynamic lo

Details Parallel binary adder having grouped stages including dynamic lo Parallel binary adder having grouped stages including dynamic lo

1988-12-14

1989-08-15

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

048581674

ABSTRACT:
A binary adder circuit is described using dynamic transistor logic in which for high speed carry propagation the adder stages are grouped in pairs or larger numbers and additional dynamic logic means is provided in each group to control a single transistor connected in series in the carry propagation path over the group. The transistors used in the specific embodiments are MOS transistors, but some or all of these could be replaced by junction FET's or bipolar transistors.

REFERENCES:
patent: 3728532 (1973-04-01), Pryor
patent: 3925652 (1975-12-01), Miller
patent: 4425623 (1984-01-01), Russell
patent: 4584661 (1986-04-01), Grundland
patent: 4623981 (1986-11-01), Wolrich et al.
patent: 4685079 (1987-08-01), Armer
Schmookler et al., "Group-Carry Generator", IBM Tech. Disclosure Bulletin, vol. 6, No. 1, Jun. 1963, pp. 77-78.
Williams, "Adder Architecture", IBM Tech. Disclosure Bulletin, vol. 23, No. 19, Mar. 1981, pp. 4587-4590.
"Pipelined Carry-Lookahead Adder for Fixed-Point Arithmetic", IBM Tech. Disclosure Bulletin, vol. 28, No. 9, Feb. 1986, pp. 4106-4108.

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