Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1981-01-28
1983-10-11
Anagnos, Larry N.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307304, 307449, 307530, H03K 3353, H03L 724
Patent
active
044094965
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
1. Technical Field
The present invention relates to an MOS integrated circuit and, more particularly, to an MOS device including a substrate bias generating circuit formed in a chip.
2. Background Art
Generally, in an n-type MOS device, a negative bias voltage is applied to the substrate thereof, in order to suppress a source-substrate effect which affects threshold voltage and, in addition, in order to increase the operation speed of the device by decreasing junction capacitances between the substrate and each of the diffusion layers. For this purpose, one external power supply for the negative bias voltage is usually necessary. However, in recent years, a substrate bias generating circuit which is formed in a chip has been provided (Ref. U.S. Pat. No. 3,806,741). An MOS device having such a substrate bias generating circuit therein does not require the above-mentioned external power supply.
Usually, positive charges are generated in the substrate due to leakage currents through the p-n junctions between the substrate and each of the diffusion layers and due to impact ionization. The substrate bias generating circuit comprises a pumping circuit for absorbing such positive charges in the substrate. Thus, the potential of the substrate remains lower than a predetermined value. It should be noted that variation of the substrate potential occurs more or less in association with the operation of internal circuits, such as memory cells, decoders or the like.
However, in one prior art MOS device which includes a substrate bias generating circuit, the pumping operation by the pumping circuit is not in synchronization with the operation of the internal circuits. In this device, the pumping operation may be effected when the substrate potential is low. As a result, the efficiency of pumping is low, since the difference between the substrate potential and the lowest potential of the pumping circuit is small. In another prior art device, the pumping operation by the pumping circuit is independent from the magnitude of the potential of the substrate, even when the pumping operation is in synchronization with the operation of the internal circuits. In this device, the pumping operation may also be effected when the substrate potential is low. In any case, the efficiency of pumping is low and, accordingly, the average level of the substrate potential is relatively high, which invites incomplete isolation between elements, unstable threshold voltages and a low operation speed.
OBJECTS AND SUMMARY OF THE INVENTION
It is an object of the present invention to provide an MOS device including a substrate bias generating circuit with a low average level of the substrate potential.
Accordingly to the present invention, there is provided an MOS device including a substrate bias circuit, comprising: a clock generator for receiving an external clock signal and generating first and second internal clock signals; an internal circuit, connected to the clock generator, which is operated by the internal clock signals; a pumping circuit driver, connected to the clock generator, for receiving the internal clock signals and generating third and fourth internal clock signals which are in synchronization with the internal clock signals and are in opposite phase with each other; and, a pumping circuit, connected to the pumping circuit driver and driven by the third and fourth internal clock signals, for generating a substrate potential, the pumping operation of the pumping circuit being effected when the substrate potential is relatively high. In this device, the pumping efficiency is high; in other words, the quantity of charges flowing from the substrate to the pumping circuit is large since the pumping operation is effected when the substrate potential is high. Accordingly, the average level of the substrate potential can be decreased compared with those of the prior art.
The present invention will be more clearly understood from the description as set forth below with reference to the accompanying drawings.
BRIEF DESCRI
REFERENCES:
patent: 3845331 (1974-10-01), Luscher
patent: 4142114 (1979-02-01), Green
patent: 4208595 (1980-06-01), Gladstein et al.
patent: 4255677 (1981-03-01), Boonstra et al.
patent: 4311923 (1982-01-01), Luscher et al.
Jensen, "Substrate Voltage Generator Circuit", IBM Tech. Disc. Bull., vol. 21, No. 2, Jul. 1978, pp. 727-728.
Anagnos Larry N.
Fujitsu Limited
Hudspeth David R.
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