Method and apparatus for computing and implementing error detect

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G06F 1110

Patent

active

047034858

ABSTRACT:
Improved design, computation and implementation of pairs of error detection check bytes, where such bytes are appended to the end of a variable length record for data integrity check of the entire record after ECC correction, is provided. The error detection check bytes are each computed using different powers of the same companion T matrix of a degree-eight primitive polynomial used for computing associated ECC check bytes. Use of the same T matrix provides the computational convenience of a reasonable size Galois field of GF(2.sup.8), while providing long cycle length through a recurring offset within the data sequences corresponding to two members of each pair.

REFERENCES:
patent: 4447902 (1984-05-01), Wilkinson
patent: 4504948 (1985-03-01), Patel
patent: 4525838 (1985-06-01), Patel
patent: 4559568 (1985-12-01), Watanabe et al.
patent: 4562578 (1985-12-01), Odaka et al.
patent: 4630272 (1986-12-01), Fukami et al.

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